Exploiting mpical DSP Data Access Patterns amid Asynchrony for a Low Power

CADRE (Configurable Asynchronous Dsp for Reduced Energy) is a low-power asynchronous DSP (digital signal processor) architecture intended for digital mobile phone chipsets. Central to the architecture are the X and Y register banks, which supply the four processing units with the data they require and to which results are written. The register banks each require 10 read and 6 write ports to service all possible requests, leading to a large and power-hungry unit if implemented directly. Instead, typical DSP data access patterns are exploited to produce a partitioned design which offers fast and low-power operation in typical cases but also caters for worst-case patterns. Power consumption and performance results for the register bank with the DSP running typical algorithms are presented, and it is shown that the register bank consumes only 8% of total power (core and memory) in what is already a highly power-efficient system.